Packaging is the secret behind a 6 nm chip's bandwidth win
The 1.22 TB/s near-memory bandwidth of Xiaomi's AI Cube came not from a cutting-edge process but from wafer-on-wafer hybrid bonding on the X-Ring O100, a chip made on an older 6 nm node. A 1.4-micrometer pitch that fuses copper pads directly secures 2.58 million bonding points and 28,672 usable data lines, in effect widening the path about 300 times compared with a typical phone package (96 lines). The price is yield: because whole wafers are bonded before dicing, known-good-die screening is impossible and the yield becomes the product of the two wafers' yields — and accepting this trade-off during a memory shortage is itself a strategic bet. The spec list that went viral mixed up the peak figures of three chips, O100, O3 and D100; the actual Cube used a fast-slow coprocessor design in which a 3B model answers first and a 120B model wakes up only when the task is hard. It is a case worth remembering as evidence that the fix for on-device AI's bottleneck is shifting from lithography to packaging.
Key points
- Hybrid-bonding pitch of 1.4 µm, denser than TSMC volume production (about 6 µm) and HBM4 (about 10 µm)
- Wafer-on-wafer rules out KGD screening; yield becomes the product of the two wafers' yields
- 1.22 TB/s is the O100 near-memory figure; 330 tokens/s is an experimental value for the 3B model
- Decode is memory-bound, so bandwidth directly sets token-generation speed
This is a note: my own write-up after reading several sources. It has no source link; events checked against a source are kept as records.