A chip built specially to do AI calculations fast and with less power.
An AI accelerator is a chip built to do AI's main maths, multiplying and adding big tables of numbers, fast and with less electricity. Google's TPU and the NPUs in phones and laptops are well-known examples.
Narrowing the job frees room that other features would use for more multiplying units. Since AI can live with slightly less precise numbers, each calculation also needs fewer parts. When Google unveiled the TPU in May 2016, it had already used TPUs in its data centers for over a year.
Ironwood, Google's seventh-generation TPU from 2025, links up to 9,216 chips as one group. But a chip tuned for one job fits others badly: Google's own guide says TPUs don't suit high-precision calculations.
Think of it like this
You can peel a potato with an all-purpose knife, but a potato peeler is faster and easier. You can't slice bread with a peeler, though. An AI accelerator is a potato peeler for AI maths.
For example
When a laptop or phone spec sheet lists "NPU" and "TOPS", it's naming the AI accelerator inside and how many trillion operations per second it can do.
Common mix-ups
Mix-upEvery AI chip is an NVIDIA GPU.
ActuallyAlphaGo ran on Google TPUs when it played Lee Sedol in 2016. In 2025 Anthropic agreed to use up to a million Google TPUs, and OpenAI agreed to design its own accelerators with Broadcom.
Mix-upA phone with an NPU can run any big AI.
ActuallyAn NPU only speeds up the maths; it doesn't add memory to hold the model. Which chip does the work is also up to the software. There are even separate tools, like Microsoft's Foundry Local in 2026, that pick the right chip among a device's GPU, NPU and CPU.
Try it in class
For teachers at the start of a lesson — or for students working on their own.
- Question
- All-purpose chip or special-purpose chip: when is it worth building a chip of your own?
- Activity
- Read the TPU records from 2016 (E0061), 2025 (E0746) and 2026 (E0915) in order and write one line on what changed each time. In particular, use the potato-peeler comparison to explain why, in 2026, the chips for training and for running models were split in two.
Records about this
Source-checked moments from AI history.
Split training and inference silicon for the first time; a signal that the era of general-purpose accelerators is ending
A TPU for the inference era. Actual GA came on Mar 31, 2026
Disclosed the design and measured performance of the first-generation TPU, becoming the reference document for discussions of dedicated accelerators
The start of the path toward silicon dedicated to neural networks rather than general-purpose GPUs